Learn Something Old Every Day, Part XIX: Athlon XP May Be Athlon MP

Quite a while ago, I acquired a dual-socket (Socket 462 aka Socket A) board for the Athlon MP, AMD’s first entry into the multi-processor/multi-socket market. Over the course of several years, I spent quite some time searching for the board in my basement, to no avail. Until a few weeks ago I finally found it… while looking for something else, of course.

The board is a Tyan Thunder K7X Pro (S2469). It’s a nice board designed for 1U servers (it has angled DIMM brackets). The board supports up to 4GB registered PC2100 DDR DRAM (with or without ECC), it has three regular and two 64-bit PCI slots, and an AGP Pro slot. There’s an onboard ATI Rage XL graphics chip and Intel 10/100 as well as Intel Gigabit Ethernet. No onboard SCSI, which was a manufacturing option. There’s also an onboard ATA-100 controller with two channels.

The board interestingly supports both EPS12V and regular ATX (20 + 4 pin) power supplies. That is somewhat important because earlier Tyan Athlon MP boards (e.g. the very similar S2468) require ATX-GES power supplies, which are neither standard ATX nor EPS12V. And I have too many oddball PSUs already.

Unfortunately, Athlon MP processors are nowadays rather difficult to find at a reasonable price or at all, and they are even more difficult to find in pairs. So I ended up with one Athlon MP 1800+ and also several Athlon XP 1800+ processors.

It is well known that Athlon XP and Athlon MP processors used the exact same core and it was possible to convert Athlon XP CPUs to the MP variant by restoring a bridge that was laser-cut during manufacturing. This hack was known at least since 2003.

It is not clear to me that AMD ever released any Athlon MPs or XPs with CPUID 660h/661h (Family 6, Model 6, Stepping 0 and 1). If so, the XP and MP models would have been indistinguishable from each other.

For the updated Athlon Model 6 with CPUID 662h (Revision A5), AMD added a CPUID bit identifying the CPU as “Multiprocessing Capable”, kind of. This was bit 19 in the extended feature flags (CPUID leaf 8000001h, register EDX).

However, AMD’s CPUID document (Publication #20734 Revision T from January 2002) includes this rather curious footnote for bit 19 of the extended feature flags: AMD reserves the right to report a “0” or a “1” for all other model 6 processors which are not tested, supported, or intended by AMD to be used for operation in multiprocessing platforms.

In other words, the Multiprocessing Capable flag (bit 19) will be definitely 1 on Athlon MPs with CPUID 662 or later, but it may be 1 on Athlon XPs as well. Which means that software cannot distinguish between an Athlon MP and an Athlon XP with the Multiprocessing Capable flag set.

Why AMD would confuse things like this is not clear. However, there is clear evidence that AMD’s CPUID note is right, and Athlon XPs may or may not set the Multiprocessor Capable CPUID flag.

As mentioned in the XP to MP conversion article, the key is the L5 bridge on the CPU. For newer K7 Athlons with the Thoroughbred and Barton cores, the bridges are described in great detail here, including the L5 bridge. I believe that the L5 bridge worked the same way on Palomino processors as well. First let’s take a closer look at those bridges.

Configuration Bridges

It is apparent that AMD used the bridges so that CPUs could be packaged, binned, tested, and then configured to report the right multiplier and voltage identifier (VID). However, the bridges were also used to turn a processor into a Duron, Athlon, or Athlon MP, and also determined “desktop” vs “mobile” identification.

The only functional difference between Athlon XP and MP that I could find from comparing the datasheets is that the latter supports ECC. However, if ECC is not enabled in the system, that can hardly make any difference. Even if ECC is enabled, a modified Athlon XP might work just fine, but it was presumably not tested and the ECC support could theoretically be faulty.

In fact, some AMD CPUID documents name the above mentioned extended CPUID bit 19 as ‘ECC’, which is surely not a coincidence (only to complicate things, the bit may have a different meaning on Sempron processors with 333 MHz and faster FSB). Note that bit 19 got de-documented circa 2005 and only appears as “reserved” in current AMD CPUID documentation. The bit was apparently never used by Intel and also wasn’t used by AMD Opteron (K8) and later processors.

XP or MP?

I have a small selection of Athlon MPs and XPs. On Athlon MPs, the L5 bridge has the middle two (out of 4, numbered 0 to 3) conductors cut, that is, conductors 1 and 2 are cut. On Athlon XPs, conductors 1, 2, and 3 are cut. Except on some Athlon XPs, only conductors 1 and 2 are cut, exactly like on an Athlon MP!

For comparison, this is what the L5 bridge looks like on a “real” Athlon XP which does not report any multiprocessing capabilities:

That is to say, some Athlons were labeled XP but were in fact functionally indistinguishable from an equivalent Athlon MP. The confusion seems to apply only to Palomino (Model 6) Athlons. According to newer AMD CPUID documentation from September 2004, Thoroughbred (Model 8) and Barton (Model 10) Athlons consistently set the Multiprocessing Capable (aka ECC) CPUID bit as one on Athlon MP and zero on Athlon XP.

Note that Duron processors were apparently affected as well. Palomino Duron CPUs (Model 6 or 7) may or may not set the Multiprocessing Capable CPUID bit.

Identifying Athlon MP

From the above it should be apparent that identifying an Athlon MP in software is difficult to say the least. Older Athlon MPs (CPUID 660h/661h) do not offer anything at all to distinguish them in software. Newer Palomino Athlon MPs with CPUID 662h do, but some Athlon XPs may look identical.

I could not find any evidence that Athlon MPs with CPUID 660h or 661h were ever released. According to cpu-world.com, even the earliest 1000 MHz Athlon MPs were already revision A5 with CPUID 662h.

The processor identification issue is further confused by the fact that firmware must program the right processor identification string into the processor. That is quite logical: Since the bridges are used to configure a CPU, the processor itself only contains a generic name string. The firmware must in effect figure out how the bridges are set up and derive the correct processor name string from that information.

For detecting multiprocessor capable CPUs, AMD offers curious advice in their December 2005 CPUID document: If the Northbridge of the platform’s core logic is an AMD-762™ controller (IGD4-2P), the processor is operating in a multiprocessing (workstation/server) platform.

In other words, multiprocessing capability might not be determined based on the actual CPU, but rather on the platform. Users are trusted to only install Athlon MPs in dual-socket platforms. A CPU which may be reported as “Athlon MP” in a dual-socket system could be an “Athlon XP” in a single-socket system.

BIOS on the Tyan S2469

The BIOS on my Tyan Thunder K7X Pro is somewhat schizophrenic. In the POST and boot summary screens, it always identifies the processor as Athlon MP. However, the actual name string programmed into the CPU may be “Athlon XP”, at least for Model 6 Athlons without bit 19 (the ECC bit) set.

The BIOS also checks that the ECC bit is set before enabling multi-processing. If both processors do not have the ECC bit set to indicate multiprocessing support, the BIOS complains and refuses to enable SMP:

When both processors have the ECC bit set (whether they are labeled as Athlon MP or Athlon XP), the BIOS boots without complaints:

What’s What?

It is possible to distinguish “true” Athlon XPs from their MP-like brethren in software. The MP-like specimens will have the ECC aka Multiprocessing Capable bit set in extended CPUID (the feature is called ‘mp’ in Linux /proc/cpuinfo).

Even better, it is also possible to distinguish the MP-capable Athlon XPs by visual inspection, as shown in the photos above. The L5 bridge is clearly labeled and visible on the top side of the CPU. If only the middle two connections are cut, the processor reports the Multiprocessing Capable (ECC) bit. If the rightmost three connections are cut, the ECC bit will be clear and the CPU identified as an Athlon XP regardless of the platform it’s in.

It is possible that the confusion is really a terminology issue, reflected in the fact that the CPUID bit that’s supposed to distinguish between Athlon XP and MP is called both “ECC” and “Multiprocessing Capable” in AMD documentation. While the CPUID bit was in practice used to check whether a CPU is MP-capable, in reality the bit indicates whether the CPU supports ECC or not. However, ECC has nothing to do with multiprocessing, except that MP-capable processors intended for workstations and servers generally support ECC, while desktop CPUs often don’t.

Perhaps early in the Palomino production run AMD tested all processors for ECC functionality, and the L5 bridge was configured to reflect that, rather than multiprocessing capability.

It is plausible that the real difference between Palomino Athlon XPs and MPs was not so much functionality as the fact that the MP parts were binned to have a lower TDP and higher temperature grade.

As seen in this table, Palomino Athlon MPs were all rated for 95°C while Athlon XPs had a 90°C rating. At the same time, AMD limited the TDP of Athlon MPs to 66W (Palomino) and later 60W (Thoroughbred/Barton) while Athlon XPs could go above 70W. This was no doubt done in order to keep problems with power supply and especially cooling of dual-socket systems under control.

Finally all Athlon MPs used 266 MHz FSB, even Bartons which normally used 333 or 400 MHz FSB in the Athlon XP variant. That was no doubt done because the only northbridge that supported Athlon MPs, the AMD-762 chip, only supported 200/266 MHz FSB.

How Common Was This?

It is obviously very difficult to say how many Athlon XPs were in fact configured to report themselves as multiprocessing capable. The only data point I have is that out of nine Athlon XP 1800+ processors randomly acquired on eBay, seven are MP-capable. This was determined by visual inspection (L5 bridge) and a CPUID check (ECC bit is set, software may report that the CPU is an Athlon MP even if the string programmed by BIOS is Athlon XP).

I don’t know if most Palomino Athlon XPs were really Athlon MPs in disguise. But it’s entirely possible that maybe half of them or more were configured as MP-capable. In any case, the MP-capable Palomino Athlon XPs do not appear to be rare.

Based on the production dates of the few CPUs I have, it is possible that earlier Palomino Athlon XPs made in late 2001 and early 2002 were often or always configured as MP-capable, or maybe really ECC capable, while Palomino Athlon XPs made sometime in the second quarter of 2002 and later were consistently not MP-capable. I do not have solid evidence for this theory, but it would make sense if MP-enabled/ECC-capable Athlon XPs were a mistake that AMD corrected later in the production run.

In my small sample, Athlon XPs with steppings AGKGA, AGNGA, and AGOGA are configured as MP capable, while the two specimens with AGOIA stepping are not. That may or may not be a coincidence; I don’t have a large enough sample to make any real conclusions.

Summary

For older Socket 462 Athlons (Palomino), distinguishing between MP and XP variants in software is a fraught process.

Older PGA Athlons offer no software-visible distinction at all. Firmware and software can only check whether the platform is MP-capable (if the northbridge is an AMD-762 chip, the only chipset supporting dual Athlon MPs) and hope that the user installed the correct CPU.

Newer (Revision A5) Palomino Athlons do have a CPUID bit (ECC) which is set on all Athlon MP processors. However, for unclear reasons, the bit is also set on many early Athlon XP processors, which are then indistinguishable from Athlon MP-labeled CPUs in software. It is unclear what functional difference, if any, there is between Athlon MPs and equivalent Athlon XPs configured to report ECC support.

Newer Socket 462 Athlons (Thoroughbred and Barton) should not suffer from this problem; the ECC CPUID bit value ought to exactly correspond to the MP/XP designation.

Update: After writing this post, further information came to light regarding ECC support in K7 processors. To summarize, Slot A Athlons always supported ECC. For Socket 462 processors, AMD decided to make ECC support optional, and ECC capability was advertised via extended CPUID bit 18, never officially documented. For Model 4 (Thunderbird) Athlons, AMD quietly deleted information about ECC support from the datasheet. For Athlon XP, ECC support was never documented.

A marketing decision was made to tie ECC support to multiprocessing capability, advertised by CPUID bit 19. However, there is no actual technical difference between MP-capable and “regular” Athlons, since they all have a built-in local APIC and the same bus interface. The real difference is ECC support. That may be how some CPUs other than Athlon MP ended up with bit 19 set.