Lies, Damn Lies, and Wikipedia

While researching the history of 486s for a previous article, I came across a fascinating Wikipedia entry and its associated talk page. It’s a nice showcase of inmates running the asylum, and a reminder that Wikipedia can’t be considered an authoritative source of information because the quality of encyclopedia entries is wildly uneven. It’s not all bad, and it could be argued that the average is quite good, but there’s no minimum quality guarantee.

Even now the 486SX article contains demonstrably incorrect claims such as this: The FPU upgrade device was shipped as the i487, which was a full blown i486DX chip with an extra pin. The i487 was installed in an upgrade socket and the extra pin was either a power or ground pin that indicated that the i487 was installed. That signal was used to disable the i486SX when the i487 was installed. 

Well, no—there is an extra pin, but it has no electrical function whatsoever. It merely prevents the chip from being installed incorrectly. And there is a pin (NC#) indicating that an upgrade processor is present designed to “shut off” the original CPU, but it is one of the standard 168 pins. The text conflates facts and turns them into a falsehood. The pins are publicly documented in Intel datasheets and it’s not so hard to find the actual information.

Then there is just plain BS like this: Back in the early 1990s, common wisdom held that it wasn’t advantageous for most users to have an FPU. Thus, many typical household applications already in existence like word processing and email were designed specifically to avoid using floating point operations.

Let’s not even discuss wether email was a”typical household application” in the early 1990s. But no, it was not “common wisdom” that most applications shouldn’t require an FPU, it was a reality of the market. FPUs were a separate item costing several hundred dollars and most PCs didn’t have any. Only a complete moron would write a word processor requiring an FPU under those conditions. That naturally led to a feedback loop and most users had little incentive to buy an expensive FPU that wasn’t going to bring any benefit.

In fact Intel was apparently making such a killing selling FPU upgrades (to the spreadsheet and CAD users who did benefit) that at least four companies designed and marketed compatible 287 and 387 replacements (IIT, ULSI, Cyrix, C&T). A clear indication that FPUs were rather overpriced.

But let’s get back to the claim that most of the talk page is about: All early 486SX chips were actually i486DX chips with a defective FPU. If testing showed that the central processing unit was working but the FPU was defective, the FPU’s power and bus connections were destroyed with a laser and the chip was sold as an SX; if the FPU worked it was sold as a DX.

There was always a rumor that 486SX processors were DXs with faulty and disabled FPU. But it was just that, a rumor, because Intel of course never stated what the real story was.

There was at least one compelling reason for the rumor: The early (1991-1992) 486SX processors had the same die size as their 486DX brethren. That was not the case for newer (since approx. late 1992) 486SX processors which had visibly smaller die compared to their DX counterparts.

Older Intel 486SX (left), 486DX (center), and newer 486SX (right).

Older Intel 486SX (left), 486DX (center), and newer 486SX (right).

There was however at least one good reason to doubt the rumor—the timeline never made any sense. The 486DX started shipping in volume in late 1989. The 486SX was only introduced in mid-1991. In the first 18 months or so when yield problems would have been the worst, there was no SX.

The Wikipedia talk page gives a very plausible, if impossible to officially confirm, alternative explanation, from someone claiming to have worked on 486 development at Intel at the time: The SX and DX chips were initially indeed the same (almost), but there was never any rebranding of chips with broken FPU. All along the i486 DX had a mechanism which allowed the FPU to be permanently disabled after production. The SX chips had the FPU disabled that way and the coprocessor part was never tested at all (so it might or might not function correctly).

There is another supporting argument for the alternative story: The CPU identification. Amusingly, the Wikipedia editor was utterly unaware and outright refusing to believe that all 386 and 486 processors have a way to return their “CPU ID”, but only immediately after reset. Newer chips return the same information as part of the family/model/stepping data through the CPUID instruction.

The point is that apart from the FPU, there is one difference between SX and DX chips: The model designation. All 486s are members of family 4, but old DX chips return model 0 while SX chips indicate model 2. The stepping information is not directly comparable either. There is no evidence that the CPUID information is adjustable after production which means the chips were manufactured as either SX or DX.

There is a related story. A naive programmer might think that the FPU-related bits in CR0 could distinguish between 486 SX and DX processors. Robert Collins wrote about this and mentioned that although Intel datasheets indicate different behavior of the CR0.ET bit on SX and DX parts, in reality the chips all behave the same. OS/2 Museum’s internal testing confirms that—CR0.ET and CR0. NE bits behave identically on 486 SX and DX processors.

The ET bit is hardwired to 1 (indicating a 387-style FPU), and the NE bit can be freely toggled, enabling internal FPU exception delivery even on SX chips with no FPU. It would be logical for SX parts to prevent the CR0.NE bit to be set… but that simply isn’t the case. Obviously the Internet can’t be trusted (with the sole exception of this blog).

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37 Responses to Lies, Damn Lies, and Wikipedia

  1. random lurker says:

    However, now your blog post is a source on the Internet equally as valid as any other, and somebody could just as well modify the article, citing this blog 😉

  2. Richard Wells says:

    The 486SX rumor of being 486 chips with disabled FPUs isn’t too outlandish. First, some 1989 486s were recalled because of a FPU error.* Second, if you read Intel’s presentations (1990) on how testing was done on the 486, there are suggestions that partially defective chips will be sold with faulty features fused off. I fully expect that Intel handled 486 production the same as all current chips are done. Test and move defective products down market as problems are located then fuse off good chips to fulfill orders that can’t be served with exclusively partially failed chips.

    * I think some of the early 486 chips with the sine/cosine bug remained in servers. At least according to the magazines at the time. I wonder if other 486s with FPU issues were sold in the time before the formal introduction of the SX. Demand far exceeded supply in 1990.

    Even with a coprocessor, software with limited needs to use floating point was often better served by ignoring it. It took longer to send to and return from the FPU than to have the integer CPU to approximate the result.

  3. Michal Necasek says:

    The mind boggles 🙂

  4. Michal Necasek says:

    No, it’s not outlandish, but does it fit the available data? The gap between i486 and SX introduction is too great. And is there evidence that Intel could change the chip’s CPU ID after production?

    I would expect that the number of chips with faulty FPU but otherwise in 100% working order simply wasn’t big enough, and the SX was meant to be a volume chip. So in 1990, Intel had zero interest in selling cheap 486s when they could charge a premium instead. In 1991, they could produce enough 486 chips that the SX made economic sense, but they needed a lot of those chips.

    Of course both could be true. Intel could be manufacturing most SXs as SXs but also rebranding DXs with defective FPUs. The key question is whether Intel could change the model and stepping information after production at the time.

    So who wants to pop open one of those old SX processors and look for the magic bond wire? 🙂

  5. Richard Wells says:

    Look at what Intel does today: fusing off cores, cache, and features after testing and then modifying the identifier to indicate the changed state. One die yielding many different CPU configurations. With the 486, it is even easier since the early 486s didn’t have a CPUID instruction so there was nothing to modify.

    Before the SX, I know of financial companies got large numbers of 486 servers at a time when the trades were reporting a lack of 486 availability because of the FPU bug. Don’t need a FPU with a database server. Now, I can’t prove these had chips with busted FPU units; I doubt they would have let me shut down operations to test FPU operations.

    After the SX was announced, there were severe shortages of 486SX-20 but no problems getting 486DX-33. The only way slower CPUs would have problems reaching market is if most production was sold at higher speed grades; with the SX being the slower 486s, that can only happen if the 486DX and 486SX are built off the same die in the same fab.

    Online verification of some of this can be found in the Oct 13, 1992 issue of PC Magazine page 116 and Dec 31, 1991 PC Mag page 162.

  6. Pavel Zagrebin says:

    I don’t know defective or not, but fact is – early 486SX have FPU on die and overall layout identical to 486DX.
    Delid your SX411 and find a FPU =)

  7. Michal Necasek says:

    I think there’s no disagreement there 🙂 I fully expect to find a disabled FPU under the lid.

  8. Michal Necasek says:

    Wrong. There’s no CPUID instruction but there is a CPU ID. DX register after reset. There are utilities to show the value (on certain boards), some BIOSes can report it via INT 15h, and some show it on the setup screen (MR BIOS). Check this page — SX and DX chips had different IDs. The table exactly matches all the 486s I checked myself.

    I know what Intel is doing today, but were they doing the same thing 25 years ago? Hard to prove one way or another. What would be the equivalent with, say, Pentiums?

    Lack of availability doesn’t mean anything without knowing the demand. If Intel made 12,000 SXs and 2,000 DXs but market wants 15,000 SXs and 2,000 DXs, the SXs will be in short supply despite being manufactured in much higher numbers but there will be no spare DXs to be resold as SXs. Doesn’t mean you’re wrong, just that what was or wasn’t unavailable doesn’t say much about what Intel produced and how.

    Just to be clear, I don’t think there’s any disagreement that early SX and DX 486s were built the same way. The only question is whether Intel made all chips the same and turned some DXs into SXs after testing, or made SXs and DXs with nearly but not quite identical masks and disabled the SX FPU without testing it for functionality.

    Internet/press rumors claim the former. Someone claiming to be an Intel test engineer says it’s the latter (and specifically makes the point that the CPU ID was hardwired). I guess you could prove the former by opening a 486SX, re-enabling the FPU, and seeing if the CPU ID changes. If the CPU ID also changes, DXs were turned into SXs after production. If it does not, chips were made as SX or DX and disabling the FPU is separate. Checking whether the FPU is fully functional could be difficult.

  9. Michal Necasek says:

    Do you know if someone already compared the SX and DX dies/packages in detail and could identify the bond wire disabling the FPU?

  10. Richard Wells says:

    I found a purported image of the early 80486SX die which includes FPU and is labeled 80486 on die. If accurate, seems fairly conclusive that at least one full 486 chip was sold as a 486SX.

  11. Michal Necasek says:

    Cool pics, but they don’t tell us much. I don’t think there ever was any question that early SXs were nearly identical to DXs. The only question is whether they were manufactured as DXs and turned to SXs later, or manufactured as SXs with some tiny tweak of the mask. To answer that, someone would have to turn an SX back to DX by re-enabling the FPU, and then check the CPU ID. Does the CPU ID also change to indicate DX, or does it stay as SX?

  12. Richard Wells says:

    CPUID should report nothing as the chip was made about a year before the CPUID instruction existed.

    The on die labeling should have been changed if Intel was running two slightly different designs. Takes about 30 seconds at layout but necessary to determine if chips reported by customers as having failures in FPU are SX chips mistakenly sent into the DX stream, damage in transit, mistakes in testing, or installed in some of the flawed motherboards that didn’t support FPUs*.

    To test, one would need to repair the cut fuse link** then extract the die and place the die in a proper 486DX ceramic shell. The plastic SX carrier has a number of pins not connected including the FP error signal pin which might make FPU usage a challenge. The FPU power requirements are probably a bit more than plastic carriers can handle. Only could determine something if the CPU had a fully working FPU; it would take considerably more information than presently available to tell the difference between a defective FPU and a designed non-functional FPU.

    * Check out comp.arch for a couple of posts by a then Amdahl employee who found several motherboards that did not support 486 FPUs.

    ** If the fuse link technique was used back then.

  13. dosfan says:

    You do realize that all Intel 32-bit processors return the family, model and stepping info in EDX upon reset don’t you ? This is well documented in the Intel developer manuals. Therefore in theory a 486DX should be distinguishable from a 486SX since they should have different model numbers.

    EDX bits 8-11: family
    EDX bits 4-7: model
    EDX bits 0-3: stepping

    Some BIOSes saved this info for later use. CPUID was added (originally on the Pentium and later backported to the 486 DX2/DX4) to return this info at any time.

    Obviously 486 motherboards didn’t originally support an FPU since there was no need (not counting Weitek) until the 486SX came along. Also who cares what an Amdahl guy had to say unless he was talking about System/370 mainframes.

  14. Richard Wells says:

    @dosfan: The bug on these motherboards meant the FPU inside the 80486 would not work effectively turning any 486DX into a 486SX. The explanation of the bug and how it relates to motherboards handling interrupts and the floating point exception pin is included in a thread marked “Beware! Common 486 motherboard bug” in comp.arch April 20, 1992. The estimate was about half of the motherboards available in 1992 would not be able to use floating point on a 486.

  15. Michal Necasek says:

    There is a world of difference between “FERR# handled incorrectly” and “no FPU”. I’m not sure you realize this but a significant chunk of software that uses the FPU (in my estimation the majority) masks exceptions anyway.

    I’m willing to believe that many boards got the math error handling wrong, because that is not something users would immediately notice (or possibly ever). I am not willing to believe for a second that the FPU was somehow disabled and no one noticed.

    To the best of my knowledge, it is not possible to externally disable the 486 FPU. If you have evidence to the contrary, I would like to see it.

  16. Michal Necasek says:

    You’re not listening. I am not talking about the CPUID instruction. I’m talking about the CPU ID, which every 486 has. Please read this again and look especially at the table near the end.

  17. Michal Necasek says:

    Here, maybe this will help: That’s the Nov ’89 datasheet corresponding to the production B-step 486s. Look at section 6.5, pages 86 and 87. The “component identifier” later became known as the CPU ID, and on the CPUs that support it, matches the family/model/stepping information returned by the CPUID instruction. See the other document which shows that the CPU ID of DX and SX parts was different. The model was different and the stepping sequence didn’t match.

    Robert Collins and Bob Smith have utilities which query the post-reset CPU ID. This doesn’t work with every board/BIOS but once you find one, you can test many CPUs. Some (few) boards have BIOSes which report the information as well.

  18. dosfan says:

    What kind of motherboard bug could possibly disable the internal 486 FPU ? I don’t remember hearing about any such thing in the early 90s, frankly that assertion sounds ludicrous to me. It’s ironic this is being posted to a blog entry about Wikipedia because this comes across as the typical incorrect stuff in a technical Wikipedia article.

    – All Intel IA-32 processors return CPU ID info in EDX upon reset. Look in any Intel developer manual starting with the 386 manual.
    – There is no known way for external hardware to disable the builtin FPU such that FPU opcodes aren’t executed.

  19. dosfan says:

    By the way the 80486SX article on Wikipedia now cites this blog entry as a source.

  20. Michal Necasek says:

    That’s kind of… ironic? But now I’m afraid to look.

  21. random lurker says:

    You could say that somebody did it already on December 27th 😉

  22. Richard Wells says:

    @dosfan: If software compiled to use X87 instructions does not work on a given 486DX installed to a given motherboard, it is not much comfort that the 486 FPU is still there and possibly even drawing power. Remove 486 chip and install it to a different motherboard and then have all the same software correctly work using X87 instructions indicates problems with a motherboard not the CPU.

    I imagine someone could emulate this by clipping off FPU related pins on a 486 and seeing what happens. The result is same if the 486 does not contact the socket or the socket has traces going nowhere.

    I will note that about 6 months after this got reported, some of the major computer manufacturers shipped diagnostic testing software with their 486 models along with a sheet pointing out how to test all the functions of the 486.

  23. dosfan says:

    Explain exactly how a motherboard issue would prevent the 486DX FPU from functioning. The CPU and FPU are part of the same chip. I can see how there could be an issue with FERR handling which as Michal said was rarely used but not an issue where the FPU was somehow disabled.

  24. Richard Wells says:

    The 8087 is tied to 8259A to handle errors. The 8259A sends out the interrupt signaling the error.

    The 486 FPU freezes on an error. If the 486 FERR line is not hooked up to the 8259A, any software written to expect the 8087 error interrupt behavior will be never receive the interrupt and the 486 FPU will never unfreeze. It may be possible with such a system to have the integer unit on the 486 continue to function while the FPU part remains frozen.

  25. Michal Necasek says:

    The 8087 uses the NMI signal to report errors. The 80287 (and 387) uses the 8259A (IRQ 13) instead and the BIOS routes it such that software expecting an NMI still works.

    When an FPU exception occurs, it’s normally the next FPU instruction (or WAIT instruction) that “notices” the error and activates FERR#. If the FERR# signal is active on an 80486, the CPU is frozen until an external interrupt arrives. I assume any interrupt will unfreeze the CPU. However, until the FPU error is cleared, a FPU instruction will keep freezing the CPU. There’s also the IGNNE# signal which will ignore FPU errors, but that is normally only activated by the FP exception handler. See Intel’s AP-578 for all the gory details (it’s really not pretty, and IBM is mostly to blame).

    The upshot is that if FERR# is not properly hooked to the PIC, an unmasked floating-exception is almost guaranteed to hang the system. Emphasis on unmasked. Most software runs with FP exceptions masked because exceptions aren’t expected to occur (or they’re highly undesirable, such as the “precision loss” exception).

    What I suspect happened was that a lot of software could use the CPU just fine, and that’s why the problem was not immediately found. If the FPU was completely dead, it would probably blow up in the BIOS POST already. But if some software did use FP exceptions, it would hang the system.

    It is hard to evaluate the exact issue without knowing the precise details. It seems most people running into the problem back then didn’t understand the details either. Such is life I suppose.

  26. Cyrix Instead says:

    So is it confirmed that later 486 SX CPU’s did not have a FPU on the die at all? If so do we know what the s-spec codes are for with and without? I am aware that the gold cap is of a different size on some of these, does the smaller cap denote no FPU at all on the die?

  27. Michal Necasek says:

    I think only Intel could truly confirm that, but all evidence points that way — smaller lid indicates chips with FPU completely missing (not just disabled/broken/whatever). S-spec codes… there isn’t even any official list, so that’s tough. This is probably the closest thing:

    At a guess, the B0 and later 486SX steppings were entirely FPU-less. That is a completely wild guess.

  28. Cyrix Instead says:

    I wonder if the SL-enhanced features added much to the die size, for example the SX798 is a later stepping(D) according to that list yet still has a large gold cap. There seem to be 4 different caps on the SX, large gold, rectangular small, square small & large black(this appears to be late production). None of the small rectangular have SL-enhanced features. SX790 & SX930 are SL and are small square gold cap.I wonder if a die shrink may explain?
    This page is handy for a quick visual check.

  29. Michal Necasek says:

    The SL stuff should add very little IMO, SMM is not that complex. And yes, there was a die shrink somewhere, I think for example all(?) DX4 CPUs have a smaller die even with twice the L1 cache.

  30. I was at Intel from 1988 – 1999. I was the product engineer for the first two versions of the 486SX. I was also “awitko” the author in the Intel 80486SX wikipedia talk pages arguing that the wikipedia article was wrong.

    The only difference between the 486DX and the original 486SX was the bond wire disabling the FPU and the CPUID. The FPU was not tested.

    The second version of the 486SX was based on the next generation process (P650) – the compaction of the original 486DX — but it also had some bug fixes (I was the one that implemented them) that had been outstanding errata since the last stepping of the 486DX compaction. It had lower TDP and therefore could be put in a plastic PQFP package. It also had a disabled FPU that was not tested. I was the PE that released the test programs for both of the first two versions.

    The third version of the 486DX was also on P650 and had the FPU removed.

    As I mentioned in the article, our yields at the time were excellent. This was motivated by price segmentation. We could go after the low end of the market with a lower price device while not compromising pricing on the flagship product.

    Another reason the defective FPU story does not make sense:

    A large percentage of defects are fatal to the basic functionality of the device. It’s very unlikely that a defect on a device would be so precise that it would affect functionality of the FPU but have no affect on any other operations. Another issue is reliability. If the FPU had some unknown defect that today affected the functionality of the FPU, it would be impossible to be sure that it would not introduce quality and reliability problems over time. We did not laser cut lines except in the silicon debug process (engineering units). We could not completely isolate the FPU through laser cutting and certainly not for production units.

  31. Michal Necasek says:

    Thanks for this information! Your posts on Wikipedia highlighted the problem with maybe Wikipedia in general and certainly with unreasonable (to put it mildly) editors — published but factually incorrect information is preferred to unpublished but correct information.

    For my reference, this page mentions the P650 process, 0.8 µm. The predecessor process was P648 at 1.0 µm and that’s what the early 486s used.

    Now a question occurs to me, did the disabled FPU lower the TDP enough for PQFP-packaged 486SX to be made? Or did the second-gen 486DX also have low enough TDP to be packaged in PQFP but Intel didn’t do that for business reasons? As far as I can tell, only SX (and SL, a different beast) chips were available in PQFP for quite a while.

    The 486SX was definitely an important chip for Intel, deployed against the 33- and 40-MHz 386s from AMD. A 40 MHz 386 vs. 25 MHz 486SX was an interesting comparison.

  32. Hi Michal.

    Thank you for finally succeeding in getting wikipedia to correct the description!

    I agree that this situation highlighted a problem within wikipedia. Editors have biases, and this editor applied a different standard to the rumors he read on the internet and even conjured up images in his head of Intel statements that never existed. An early example of “fake news”. 🙂

    Yes, that process information is correct.

    Disabling the FPU by itself would not allow the original (P648) 486SX to have a TDP compatible with the PQFP package. The required TDP was achieved by going to the P650 which was more power efficient.

    The idea was that the 486SX PQFP package could be surface mounted on the motherboard and there would be a ZIF socket for a 487 upgrade (in ceramic package). There certainly was no technical reason we could not have introduced a 486DX in PQFP package, but it would not have allowed the higher speeds of the 486DX. I think since we wanted to position 486DX at the high end and 486SX at the low end, this made sense to me.

    Yes, the AMD products were the primary impetus behind the price segmentation strategy.

  33. Michal Necasek says:

    I didn’t actually do anything — besides writing about the ridiculous situation 🙂 The fake news aspect is interesting, because the rumor about 486SX chips having faulty CPUs was fairly widespread. Intel wasn’t talking and there was not much others could have done to disprove the rumor. It’s good to have the record corrected.

    Ah yes, the PQFP CPUs were mostly lower speeds and I think almost always soldered next to a PGA socket. At some point around 1993-1994 such boards were common.

  34. Yuhong Bao says:

    “The idea was that the 486SX PQFP package could be surface mounted on the motherboard and there would be a ZIF socket for a 487 upgrade (in ceramic package).”
    Later “OverDrive” BTW.

  35. Yuhong Bao says:

    Off topic, but do anyone have old 486 errata sheets now that NDA has expired?

  36. Yuhong Bao says:

    Interestingly, it seems that not all Intel 486SL CPUs even have a FPU. I wonder whether the 386SL/486SL was the beginning of Intel’s attempt to separate desktop and laptop CPUs. Do anyone have the 486SL datasheet BTW?

  37. Michal Necasek says:

    There seems to be conflicting information about the 486SL. I see claims that a “486SL-NM” had no FPU, while a regular 486SL did have an FPU built in, although I can’t find any evidence that the 486SL-NM is not simply made up (is that NM for “No Math”?).

    There seems to have been some “low-power i486” in the 486SL time frame (datasheet 241199-002 available) which was not the 486SL. In fact I can’t find any mention of a 486SL datasheet at all; that is, not only can’t I find the actual datasheet but I can’t find any reference to it indicating that it ever existed.

    For whatever odd reason there was separate literature about the Intel486 SuperSet (“Intel486 SL Microprocessor Superset Programmer’s Reference Manual” and “System Design Guide”, the latter order no. 241326-001), and the 486SL itself apparently only lasted about six months until it was replaced by updated SL-enhanced 486 chips in mid-1993. Reading between the lines it appears that 486SL was an SL-enhanced 486 minus the Pentium features (CPUID, enhanced V86).

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