Soyo SY-4SAW2 Notes

Following is a list of notes describing several less-than-obvious features and characteristics of the Soyo SY-4SAW2 486 VIP motherboard. This is a latter-day 486 board based on the SiS 496/497 chipset, notable for PS/2 mouse support and the ability to use just about any CPU compatible with Socket 3.

Most of these characteristics and limitations are a direct consequence of the use of the SiS 85C496/497 chipset and the way said chipset is configured in the 4SAW2 board.

  • The VL-Bus slot is target only; an adapter board in this slot cannot work as a bus master. This is a chipset limitation (VL-Bus support is target only). The consequence is that bus-mastering VLB boards such as SCSI adapters won’t work, but most graphics cards will.
  • PCI slot 4 is slave only; an adapter board in this slot cannot work as a bus master. Again a chipset limitation, although in this case configurable by board designed. The consequences are much the same as above—most PCI graphics cards will work in this slot, but SCSI HBAs or network cards won’t. The other three PCI slots do not share this limitation.
  • The SIMM1 slot (closest to the board edge) can only use a single side of a memory module. Again a chipset limitation/configuration option. A double-sided SIMM in this slot will typically be detected as one half of its nominal capacity.
  • IDE and PCI pins are multiplexed. A chipset limitation—the (VL-Bus) IDE controller pins are shared with PCI address pins on the chipset package, which means that PCI cycles cannot be issued concurrently to IDE cycles. This has a potential performance impact.
  • The L2 cache may not be able to cache the entire main memory. This is a chipset limitation—the tag RAM only uses 7 or 8 bits, which limits the number of physical address bits the cache controller can handle. A 256K cache with 7-bit tag can handle 32 MB, with 8-bit tag it’s 64 MB. Halving the cache size halves the size of cacheable memory, doubling the cache size doubles it.
  • The L2 cache can be interleaved (a chipset design choice). If it is, the cache is somewhat faster. Whether interleaving is used usually depends on the size and type of cache SRAM chips used.
  • Main memory access is not interleaved. This is a chipset limitation. As a consequence, memory modules can be mixed in any manner without a performance impact. However, the board may not be as fast as systems with interleaved memory support.
  • Although the SiS chipset should support EDO RAM, the board doesn’t appear to. This may be a BIOS limitation. The board manual makes no mention of EDO support.
  • The turbo switch must be engaged (shorted) for the board to run at full speed.

And one performance note: The SiS chipset’s cache controller is relatively slow at handling cache misses. That means most programs which measure main memory speed report very low figures (around 12 MB/s for reads vs approximately 30 MB/s for writes). When L2 cache is disabled, the read speed matches the write speed… but it’s of course still much slower than a cache hit.

Write-Back Enhanced IntelDX4 in the 4SAW2

The board’s manual does not describe the jumper settings required for Write-Back Enhanced DX4 processors from Intel. While such processors work when jumpered as regular Intel DX4, the write-back cache will not be utilized (and hence the CPU will in fact behave exactly like a regular DX4).

Contrary to popular belief, the write-back cache on the Intel DX4 is not something software (including firmware/BIOS) can configure. To enable write-back caching, the WB/WT# processor pin must be driven high when the processor is reset. One way to achieve the desired results is jumpering the 4SAW2 board for a P24D processor (Intel DX2 processors with write-back cache) but setting the frequency and voltage jumpers for a DX4 (3.45V).

The way to unambiguously check whether a write-back cache is used or not is a little odd: The processor changes its model number reported through CPUID. The family will be always 4 (for 486), but the model will be 8 for standard DX4 processors and 9 for write-back enhanced DX4 processors with write-back caching in use.

For reference, a 100 MHz Intel DX4 processor shows a score of 197.1 in Norton Utilities 8.0 SYSINFO in the 4SAW2 board. That is true for both a standard DX4 and a write-back enhanced DX4 with standard write-through L1 caching. With write-back cache in use, the same CPU shows a score of 215.0 (slightly better than a 66 MHz Pentium).

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8 Responses to Soyo SY-4SAW2 Notes

  1. Yuhong Bao says:

    Also don’t forget the PSE support with write-back DX4s.

  2. Michal Necasek says:

    I deliberately didn’t mention it because it’s irrelevant to caching.

  3. George says:

    Hello friend,
    if you still have got your Soyo SY-4SAW2 486 mobo and a litlle time to help, I would be very grateful to you ! I am fresh owner of identical motherboard, but my one was crippled by some “motherfucker” who cut main voltage regulator transistor off this board.
    I would like to try solder its back and take this nice motherboard back to life, but I don’t know what type of voltage regulator should be used there.

    So if you have option to check type of this transistor :
    and tell me, that’d be great 🙂

    With friendly greetings George from Czech republic

  4. Michal Necasek says:

    Ahoj Jirko,
    The VRM on my 4SAW2 is a Sharp PQ30RV21. The datasheet is available so it should also be possible to find a different part with the same specs.

  5. George says:

    Ahoj a super – thanks for information and your help ! Will try to find out right Sharp one and take mobo back to life ! 🙂

  6. feipoa says:

    I generally have had trouble using 4 PCI cards in a SiS 496-based motherboard. I’ve tried a USB 1.1 and a PCI graphics card in the 4th PCI slot and they did not work, even after disabling the onboard PCI IDE controller. I was testing with a full house, that is, all 4 PCI slots filled.

    In my opinion, the main limitations of the Soyo SY-4SAW2 are,

    1) single-banked cache. Singled-banked cache cannot interleave. This is not usually a problem for the average user, but for those who want to run the FSB at 40 MHz may notice that you can no longer use the fastest cache timings in the BIOS and maintain a stable system. This is especially true when using 512 KB of cache (single-banked). Generally, double-banked cache can handle faster cache and memory timings, especially 256 KB double-banked. With single-banked cache, you are also limited to 512 KB of cache as opposed to 1024 KB with double-banked cache. This is normally not an issue for most users, but if you are wanting to run 128 MB of RAM with the cache in write-back mode, you will need 1024K to cache all of your RAM. This much RAM may be of benefit for the die hard crazy individual still using NT4 to browse the web in the early 2000’s (me!). There are other SiS 496 boards with PCI/ISA only slots and 1024K which perform well.

    2) the board contains a VLB slot. It was demonstrated in another forum that SiS 496 boards which contain PCI and VLB slots have, both, reduced VLB and PCI performance.

    In response to some of your comments.

    I have several SiS 496-based motherboards and they all work fine with four 32 MB sticks of double-sided FPM. Not sure why this Soyo board needs single-sided in the last SIMM slot.

    While the PS/2 mouse header is a nice bonus, most SiS 496-based boards with a 40-pin DIP keyboard controller can be modified to have native PS/2 mouse support. I modifed several boards, e.g. MSI 4144, Chaintech 486SPM, and DTK PKM-0033S for PS/2 mouse support.

    Although the SiS 496 board does not do memory interleaving, it still has the fastest memory throughput of all late era PCI 486 motherboards. The only mainstream PCI 486 board I know of which has memory interleaving are those based on the Intel Saturn II chipset. Tests have shown that the memory throughput and overall performance of the Saturn II’s memory are below that of the SiS 496.

    I have not witnessed any performance benefit of interleaved cache vs. non-interleaved cached on the SiS 496 or any other PCI-based 486 motherboard for the same CMOS timings utilised. The speed benefit of interleaved cache vs. non-interleaved cache appears to come from the ability use faster cache timings for interleaved cache systems vs. non-interleaved and still maintain a stable system. I believe some BIOSes may adjust the CMOS cache timings automatically depending on if you have double-banked (interleaved) or single-banked (non-interleaved) cache.

    Very few SiS 496 boards work stable with EDO RAM. I recall reading about one particular late revision of the SiS 496 chipset which supposedly works with EDO RAM though. It may have been the revision with “PR” written on the surface. None-the-less, it has been my experience that using FPM memory on 486 motherboards, even those which support EDO, e.g. MB-8433, tends to allow for faster memory and cache timings.

  7. Hinoserm says:

    I’ve learned something interesting — the unpopulated jumper JP19 (near the three resistor banks just next to the SIS 496) on the SY-4SAW2 board is what would normally connect RAS1 and RAS3 lines on the BANK3 SIMM slot to the chipset — but it’s disconnected and unpopulated by default.

    Adding a header and a jumper between pins 1 and 2 on JP19 allows my board to use double-sided SIMMs in all four slots — contrary to the manual and the default configuration. I have not yet encountered any issues doing so, and I’m really not sure why they made this design choice.

  8. Michal Necasek says:

    That is very interesting. I wonder why there would be a jumper for that in the first place? Some problem with electrical loading, some modules being marginal? Could be they just decided to not support it at all to avoid reliability issues.

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